1. Field of the Invention
The present invention relates to a liquid crystal display and its fabrication method, and more particularly, to a liquid crystal display and its fabrication method capable of simplifying a process.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) displays images by controlling light transmittance of liquid crystal by using electric fields. LCDs are divided into a vertical field application type LCD and a horizontal field (in-plane) field application type LCD according to the direction of electric fields driving the liquid crystals.
The vertical field application type LCD drives TN (Twisted Nematic) mode liquid crystals by a vertical electric field formed between pixel electrodes and common electrodes disposed to face each other on upper and lower substrates. Such vertical field application type LCD advantageously has a large aperture ratio but is disadvantageous in that its viewing angle is narrow as 90°.
On the other hand, the in-plane field application type LCD drives IPS (In-Plane Switch) mode liquid crystals by an in-plane field between pixel electrodes and common electrodes disposed to be parallel to each other on a lower substrate. Such in-plane field application type LCD advantageously has a wide viewing angle of about 160° but is disadvantageous in that its aperture ratio and transmittance are low.
Thus, in order to improve the shortcomings of the in-plane field application type LCD, a fringe field switching (FFS) mode LCD that operates using a fringe field has been proposed.
In the FFS mode LCD, a common electrode plate and pixel electrodes are formed with an insulation film interposed therebetween at a pixel area, and in this case, the space between the common electrode plate and the pixel electrodes is narrower than that between upper and lower substrates to form a fringe field. Liquid crystal molecules filled between the upper and lower substrates operate to thus improve an aperture ratio and transmittance.
FIG. 1 is a sectional view showing a schematic construction of the FFS mode LCD according to the related art. FIGS. 2a to 2e are sectional views showing the sequential processes of fabricating the FFS mode LCD. The related art FFS mode LCD and its fabrication method will now be described with reference to FIG. 1 and FIGS. 2a to 2e. 
Referring to FIG. 1, the related art FFS mode TFT substrate includes a gate line (not shown) and a data line 4 formed to cross each other with a gate insulating layer 22 interposed therebetween on a substrate 20, a thin film transistor (TFT) formed at each crossing of the gate line and the data line, a common electrode plate 14 and pixel electrode slits 18 formed with the gate insulating layer 22 and a passivation film 28 interposed therebetween to form a fringe field at a pixel area formed with a crossing structure of the gate line and the data line, and a common line 16 connected with the common electrode plate 14.
The common electrode plate 14 receives a reference voltage through the common line 16 which is formed on the common electrode plate 14 and connected with the common electrode plate 14 at each pixel area. The common electrode plate 14 is formed of a transparent conductive layer, and the common line 16 is formed of a gate metallic layer together with the gate line.
In the TFT, a pixel signal of the data line 4 is charged in the pixel electrode slits 18 and maintained in response to a gate signal of the gate line.
For this purpose, the TFT includes a gate electrode 6 connected with the gate line, a source electrode 8 connected with the data line 4, a drain electrode 10 connected with the pixel electrode slits 18, an active layer 24 overlapping with the gate electrode 6 with the gate insulating layer 22 and forming a channel between the source electrode 8 and the drain electrode 10, and an ohmic-contact layer 26 for ohmic-contacting with the source electrode 8, the drain electrode 10, and the active layer 24.
The pixel electrode slits 18 are connected with the drain electrode 10 of the TFT via a contact hole 12 that penetrates the passivation layer 28 so as to overlap with the common electrode plate 14. Such pixel electrode slits 18 form a fringe field with the common electrode plate 14 to allow liquid crystal molecules arranged in a horizontal direction between the TFT substrate and a color filter substrate to be rotated by dielectric anisotropy. Transmittance of light that transmits through the pixel area varies according to the rotation degree of the liquid crystal molecules to thus represent gray scales.
A storage capacitor that stably maintains a video signal supplied to the pixel electrode slits 18 is formed at the overlap portion of the common electrode plate 14 and the pixel electrode slits 18.
The fabrication method of the FFS mode TFT substrate will now be described with reference to FIGS. 2a to 2e. 
As shown in FIG. 2a, the common electrode plate 14 is formed at each pixel area of the substrate 20. The common electrode plate 14 is formed at each pixel area by forming a transparent conductive film on the substrate 20 and then patterning the transparent conductive film according to a first photomasking process.
As shown in FIG. 2b, the gate line including the gate electrode 6 and the common line 16 are formed on the substrate 20 with the common electrode plate 14 formed thereon through a second photomasking process. The gate line and the common line 16 are formed such that a metallic film for the gate line is formed on the substrate 20 with the common electrode plate 14 formed thereon and then patterned through the second photomasking process.
As shown in FIG. 2c, the gate insulating layer 22 is formed on the substrate 20 with a gate metallic pattern formed thereon, and a semiconductor pattern including the active layer 24 and the ohmic-contact layer 26, and a source/drain metallic pattern including the data line 4, the source electrode 8 and the drain electrode 10 are formed.
In detail, the gate insulating layer 22, an amorphous silicon layer, an n+ amorphous silicon layer, and source/drain metallic layers are sequentially formed on the substrate 20 with the gate metallic pattern formed thereon. And then, a photoresist pattern having a step is formed on the source/drain metallic pattern through a photolithography process using a third mask, a slit (diffraction) exposure mask. The photoresist pattern having a step has a relatively lower height at a channel part of the TFT. Through the etching process using the photoresist pattern, there are formed source and drain patterns and a semiconductor pattern therebelow. Subsequently, the photoresist pattern is ashed and the exposed source and drain patterns are removed together with the lower ohmic-contact layer 26 to separate the source electrode 8 and the drain electrode 10.
As shown in FIG. 2d, the passivation layer 28 with an opening 12 is formed on the source and drain electrodes 8 and 10 and the gate insulating layer 22 through a fourth photomasking process. Namely, the passivation layer 28 is formed on the source and drain electrodes 8 and 10 and the gate insulating layer 22 and then patterned through the fourth photomasking process to form the opening 12 exposing the drain electrode 10.
As shown in FIG. 2e, the pixel electrode slits 18 are formed on the passivation layer 28 through a fifth photomasking process. The pixel electrode slits 18 are formed such that a transparent conductive layer is formed on the passivation layer 28 and then patterned through a photolithography process using a fifth photo mask and an etching process.
In the related art FFS mode TFT substrate fabrication method, a total of five masks are used, and in this case, the number of masks indicates the number of processes for fabricating an array substrate. In this case, the photolithography process accompanies several processes such as washing, and coating, exposing, developing and etching of a photosensitive film, causing a problem that much processing time is taken and a fabrication cost increases.
Thus, if only one time of photolithography process would be omitted, the fabrication time could be considerably shortened and the fabrication cost and the defect rate could be also reduced. Thus, a method for reducing the number of masks needs to be proposed.